137 lines
5.4 KiB
C
137 lines
5.4 KiB
C
/* InputCapture.c
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* Jonathan Valvano
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* June 11, 2024
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* Derived from timx_timer_mode_capture_edge_capture_LP_MSPM0G3507_nortos_ticlang
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*/
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#include <ti/devices/msp/msp.h>
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#include "../inc/LaunchPad.h"
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#include "../inc/InputCapture.h"
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#include "../inc/Clock.h"
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// input wave connected to PA12, TG0_C0
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#define PA12INDEX 33
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// dual signal waves connected to
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// PB8 ELA TA0_C0
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// PB12 ERA TA0_C1
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// G0/G8 in power domain PD0, so
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// for 32MHz bus clock, SYSCLK clock is 32MHz
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// for 40MHz bus clock, SYSCLK clock is ULPCLK 20MHz
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// for 80MHz bus clock, SYSCLK clock is ULPCLK 40MHz
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// Arm interrupts on rising edge of PA12
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// interrupts will be enabled in main after all initialization
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// timerClkSrc = 2 for 32768 Hz LFCLK
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// = 4 for 4MHz MFCLK
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// = 8 for 80/32/4 BUSCLK
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// prescale divide clock by prescale+1, 0 to 255
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// priority is 0(highest),1,2 or 3(lowest)
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/*
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* timerClkSrc could be 40 MHz, 20MHz, 32MHz, 4MHz, or 32767Hz
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* timerClkDivRatio = 1
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* timerClkFreq = (timerClkSrc / (timerClkDivRatio * (timerClkPrescale + 1)))
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* resolution = (timerClkDivRatio * (timerClkPrescale + 1)))/timerClkSrc
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* For example, source=LFCLK, prescale=255, resolution = 7.8125ms
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* For example, source=BUSCLK, prescale=19, resolution = 1us
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*/
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void InputCapture_Init(uint32_t timerClkSrc, uint32_t timerClkPrescale, uint32_t priority){
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// LaunchPad_Init();
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TIMG0->GPRCM.RSTCTL = 0xB1000003;
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TIMG0->GPRCM.PWREN = 0x26000001;
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Clock_Delay(24); // time for TimerG0 to power up
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IOMUX->SECCFG.PINCM[PA12INDEX] = 0x00040084; // TIMG0 CCP0
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TIMG0->CLKSEL = timerClkSrc; // 8=BUSCLK, 4= MFCLK, 2= LFCLK clock
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TIMG0->CLKDIV = 0x00; // divide by 1
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TIMG0->COMMONREGS.CPS = timerClkPrescale; // divide by prescale+1,
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// 32768Hz/256 = 256Hz, 7.8125
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TIMG0->COUNTERREGS.LOAD = 0xFFFF; // set reload register
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// interrupts at rising edge of PA12
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TIMG0->COUNTERREGS.CTRCTL = 0x02;
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// bits 5-4 CM =0, down
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// bits 3-1 REPEAT =001, continue
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// bit 0 EN enable (0 for disable, 1 for enable)
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TIMG0->COUNTERREGS.CCCTL_01[0] = 0x00020001;
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// CCCTL_01
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// bit 17 1 capture
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// bits 14-12 ZCOND zero condition
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// bits 10-8 LCOND load condition
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// bits 6-4 ACOND advance condition
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// bits 2-0 CCOND capture condition, 1 is rising edge of CCP
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TIMG0->CPU_INT.IMASK |= 0x10; // CCD0 mask
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TIMG0->COMMONREGS.CCLKCTL = 1;
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TIMG0->COUNTERREGS.IFCTL_01[0] = 0x0002;
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// bit 12 FE =0 bypass
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// bit 11 CPV=0 voting
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// bit 9-8 FP=00 filter period 3
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// bit 7 INV=0 noninverted
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// bits 3-0 =0010 input is CCP0
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NVIC->ISER[0] = 1 << 16; // TIMG0 interrupt
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NVIC->IP[4] = (NVIC->IP[4]&(~0x000000FF))|(priority<<6); // set priority (bits 7,6) IRQ 16
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TIMG0->COUNTERREGS.CTRCTL |= 0x01;
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}
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// Power Domain PD1
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// dual signal waves connected to
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// PB8 ELA TA0_C0
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// PB12 ERA TA0_C1
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// initialize A0 for rising edge input capture interrupt
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// for 32MHz bus clock, Timer clock is 32MHz
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// for 40MHz bus clock, Timer clock is MCLK 40MHz
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// for 80MHz bus clock, Timer clock is MCLK 80MHz
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// Arm interrupts on rising edge of PB8, PB12
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// interrupts will be enabled in main after all initialization
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// timerClkSrc = 2 for 32768 Hz LFCLK
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// = 4 for 4MHz MFCLK
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// = 8 for 80/32/4 BUSCLK
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// prescale divide clock by prescale+1, 0 to 255
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// priority is 0(highest),1,2 or 3(lowest)
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/*
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* timerClkSrc could be 80 MHz, 40MHz, 32MHz, 4MHz, or 32767Hz
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* timerClkDivRatio = 1
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* timerClkFreq = (timerClkSrc / (timerClkDivRatio * (timerClkPrescale + 1)))
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* resolution = (timerClkDivRatio * (timerClkPrescale + 1)))/timerClkSrc
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* For example, source=LFCLK, prescale=255, resolution = 7.8125ms
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* For example, source=BUSCLK, prescale=79, resolution = 1us
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*/
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void InputCapture_InitDual(uint32_t timerClkSrc, uint32_t timerClkPrescale, uint32_t priority){
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// assumes LaunchPad_Init() has been called
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TIMA0->GPRCM.RSTCTL = 0xB1000003;
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TIMA0->GPRCM.PWREN = 0x26000001;
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Clock_Delay(24); // time for TimerA0 to power up
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IOMUX->SECCFG.PINCM[PB8INDEX] = 0x00040084; // TIMA0 CCP0
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IOMUX->SECCFG.PINCM[PB12INDEX] = 0x00040085; // TIMA0 CCP1
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TIMA0->CLKSEL = timerClkSrc; // 8=BUSCLK, 4= MFCLK, 2= LFCLK clock
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TIMA0->CLKDIV = 0x00; // divide by 1
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TIMA0->COMMONREGS.CPS = timerClkPrescale; // divide by prescale+1,
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// 32768Hz/256 = 256Hz, 7.8125
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TIMA0->COMMONREGS.CCPD = 0; // CCP are inputs
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TIMA0->COUNTERREGS.LOAD = 0xFFFF; // set reload register
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// interrupts on rising edge of PB8, PB12
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TIMA0->COUNTERREGS.CTRCTL = 0x02;
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// bits 5-4 CM =0, down
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// bits 3-1 REPEAT =001, continue
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// bit 0 EN enable (0 for disable, 1 for enable)
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TIMA0->COUNTERREGS.CCCTL_01[0] = 0x00020001;
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TIMA0->COUNTERREGS.CCCTL_01[1] = 0x00020001;
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// CCCTL_01
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// bit 17 1 capture
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// bits 14-12 ZCOND zero condition
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// bits 10-8 LCOND load condition
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// bits 6-4 ACOND advance condition
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// bits 2-0 CCOND capture condition, 1 is rising edge of CCP
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TIMA0->CPU_INT.IMASK |= 0x30; // CCD1 and CCD0 mask
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TIMA0->COMMONREGS.CCLKCTL = 1;
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TIMA0->COUNTERREGS.IFCTL_01[0] = 0x0002;
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// bit 12 FE =0 bypass
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// bit 11 CPV=0 voting
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// bit 9-8 FP=00 filter period 3
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// bit 7 INV=0 noninverted
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// bits 3-0 =0010 input is CCP0
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NVIC->ISER[0] = 1 << 18; // TIMA0 interrupt
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NVIC->IP[4] = (NVIC->IP[4]&(~0x00FF0000))|(priority<<22); // set priority (bits 7,6) IRQ 18
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TIMA0->COUNTERREGS.CTRCTL |= 0x01;
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}
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