215 lines
8.2 KiB
C
215 lines
8.2 KiB
C
/* ADCTimer.c
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* Jonathan Valvano
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* December 8, 2025
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* Derived from adc12_single_conversion_vref_internal_LP_MSPM0G3507_nortos_ticlang
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* adc12_single_conversion_LP_MSPM0G3507_nortos_ticlang
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* adc12_triggered_by_timer_event_LP_MSPM0G3507_nortos_ticlang
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*/
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// ****note to students****
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// the data sheet says the ADC does not work when clock is 80 MHz
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// however, the ADC seems to work on my boards at 80 MHz
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// I suggest you try 80MHz, but if it doesn't work, switch to 40MHz
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#include <ti/devices/msp/msp.h>
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#include "../inc/ADCTimer.h"
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#include "../inc/Clock.h"
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// Assumes 80 MHz bus
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// power Domain PD0
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// for 80MHz bus clock, Timer G0 clock is ULPCLK 40MHz
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// frequency = TimerClock/prescale/period
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// e.g., period=5000,prescale=8 is 40MHz/5000/8 = 1kHz
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void ADC0_TimerG0_Init(uint32_t channel, uint32_t reference,uint16_t period, uint32_t prescale, uint32_t priority){
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// Reset ADC Timer G0 and VREF
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// RSTCLR
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// bits 31-24 unlock key 0xB1
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// bit 1 is Clear reset sticky bit
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// bit 0 is reset ADC
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ADC0->ULLMEM.GPRCM.RSTCTL = 0xB1000003;
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if(reference == ADCVREF_INT){
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VREF->GPRCM.RSTCTL = 0xB1000003;
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}
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TIMG0->GPRCM.RSTCTL = 0xB1000003;
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// Enable power ADC G0 and VREF
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// PWREN
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// bits 31-24 unlock key 0x26
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// bit 0 is Enable Power
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ADC0->ULLMEM.GPRCM.PWREN = 0x26000001;
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if(reference == ADCVREF_INT){
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VREF->GPRCM.PWREN = 0x26000001;
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}
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TIMG0->GPRCM.PWREN = 0x26000001;
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Clock_Delay(24); // time for ADC Vref G0 to power up
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TIMG0->CLKSEL = 0x08; // bus clock
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TIMG0->CLKDIV = 0x00; // divide by 1
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TIMG0->COMMONREGS.CPS = prescale-1; // divide by prescale,
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TIMG0->COUNTERREGS.LOAD = period-1; // set reload register
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TIMG0->FPUB_0 = 1; // publish on channel 1
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// bits 29-28 CVAE 00 (set to LOAD value)
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TIMG0->COUNTERREGS.CTRCTL = 0x02;
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// bits 5-4 CM =0, down
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// bits 3-1 REPEAT =001, continue
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// bit 0 EN enable (0 for disable, 1 for enable)
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TIMG0->GEN_EVENT0.IMASK = 1; // hardware event published on Chan1
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TIMG0->COMMONREGS.CCLKCTL = 1;
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ADC0->ULLMEM.GPRCM.CLKCFG = 0xA9000000; // ULPCLK
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// bits 31-24 key=0xA9
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// bit 5 CCONSTOP= 0 not continuous clock in stop mode
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// bit 4 CCORUN= 0 not continuous clock in run mode
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// bit 1-0 0=ULPCLK,1=SYSOSC,2=HFCLK
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ADC0->ULLMEM.CLKFREQ = 7; // 40 to 48 MHz
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ADC0->ULLMEM.CTL0 = 0x03010000;
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// bits 26-24 = 011 divide by 8
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// bit 16 PWRDN=1 for manual, =0 power down on completion, if no pending trigger
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// bit 0 ENC=1 enable (1 to 0 will end conversion)
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ADC0->ULLMEM.CTL1 = 0x00000001;
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// bits 30-28 =0 no shift
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// bits 26-24 =0 no averaging
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// bit 20 SAMPMODE=0 timer triggers
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// bits 17-16 CONSEQ=01 ADC at start will be sampled once, 10 for repeated sampling
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// bit 8 SC=0 for stop, =1 to software start
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// bit 0 TRIGSRC=1 timer trigger
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ADC0->ULLMEM.CTL2 = 0x00000000;
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// bits 28-24 ENDADD (which MEMCTL to end)
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// bits 20-16 STARTADD (which MEMCTL to start)
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// bits 15-11 SAMPCNT (for DMA)
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// bit 10 FIFOEN=0 disable FIFO
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// bit 8 DMAEN=0 disable DMA
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// bits 2-1 RES=0 for 12 bit (=1 for 10bit,=2for 8-bit)
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// bit 0 DF=0 unsigned formant (1 for signed, left aligned)
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ADC0->ULLMEM.MEMCTL[0] = reference+channel;
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// bit 28 WINCOMP=0 disable window comparator
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// bit 24 TRIG trigger policy, =0 for auto next, =1 for next requires trigger
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// bit 20 BCSEN=0 disable burn out current
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// bit 16 = AVGEN =0 for no averaging
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// bit 12 = STIME=0 for SCOMP0
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// bits 9-8 VRSEL = 10 for internal VREF,(00 for VDDA)
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// bits 4-0 channel = 0 to 7 available
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ADC0->ULLMEM.SCOMP0 = 0x64; // sample clocks
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ADC0->ULLMEM.SCOMP1 = 0x32; // sample clocks
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if(reference == ADCVREF_INT){
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VREF->CLKSEL = 0x00000008; // bus clock
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VREF->CLKDIV = 0; // divide by 1
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VREF->CTL0 = 0x0001;
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// bit 8 SHMODE = off
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// bit 7 BUFCONFIG=0 for 2.4 (=1 for 1.4)
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// bit 0 is enable
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VREF->CTL2 = 0;
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// bits 31-16 HCYCLE=0
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// bits 15-0 SHCYCLE=0
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while((VREF->CTL1&0x01)==0){}; // wait for VREF to be ready
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}
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ADC0->ULLMEM.FSUB_0 = 0x00000001; // subscribe to chan 1
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ADC0->ULLMEM.CPU_INT.IMASK = 0x00000100; //MEMRESIFG0
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ADC0->ULLMEM.CTL0 |= 1; // start
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NVIC->ISER[0] = 1 << 4; // ADC0 interrupt
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NVIC->IP[1] = (NVIC->IP[1]&(~0x000000FF))|(priority<<6); // set priority (bits 7,6) IRQ 4
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TIMG0->COUNTERREGS.CTRCTL |= 0x01;
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}
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// Assumes 80 MHz bus
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// power Domain PD0
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// for 80MHz bus clock, Timer G8 clock is ULPCLK 40MHz
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// frequency = TimerClock/prescale/period
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// e.g., period=5000,prescale=8 is 40MHz/5000/8 = 1kHz
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void ADC1_TimerG8_Init(uint32_t channel, uint32_t reference,uint16_t period, uint32_t prescale, uint32_t priority){
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// Reset ADC Timer G8 and VREF
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// RSTCLR
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// bits 31-24 unlock key 0xB1
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// bit 1 is Clear reset sticky bit
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// bit 0 is reset ADC
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ADC1->ULLMEM.GPRCM.RSTCTL = 0xB1000003;
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if(reference == ADCVREF_INT){
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VREF->GPRCM.RSTCTL = 0xB1000003;
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}
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TIMG8->GPRCM.RSTCTL = 0xB1000003;
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// Enable power ADC G0 and VREF
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// PWREN
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// bits 31-24 unlock key 0x26
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// bit 0 is Enable Power
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ADC1->ULLMEM.GPRCM.PWREN = 0x26000001;
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if(reference == ADCVREF_INT){
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VREF->GPRCM.PWREN = 0x26000001;
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}
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TIMG8->GPRCM.PWREN = 0x26000001;
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Clock_Delay(24); // time for ADC Vref G8 to power up
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TIMG8->CLKSEL = 0x08; // bus clock
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TIMG8->CLKDIV = 0x00; // divide by 1
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TIMG8->COMMONREGS.CPS = prescale-1; // divide by prescale,
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TIMG8->COUNTERREGS.LOAD = period-1; // set reload register
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TIMG8->FPUB_0 = 1; // publish on channel 1
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// bits 29-28 CVAE 00 (set to LOAD value)
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TIMG8->COUNTERREGS.CTRCTL = 0x02;
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// bits 5-4 CM =0, down
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// bits 3-1 REPEAT =001, continue
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// bit 0 EN enable (0 for disable, 1 for enable)
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TIMG8->GEN_EVENT0.IMASK = 1; // hardware event published on Chan1
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TIMG8->COMMONREGS.CCLKCTL = 1;
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ADC1->ULLMEM.GPRCM.CLKCFG = 0xA9000000; // ULPCLK
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// bits 31-24 key=0xA9
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// bit 5 CCONSTOP= 0 not continuous clock in stop mode
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// bit 4 CCORUN= 0 not continuous clock in run mode
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// bit 1-0 0=ULPCLK,1=SYSOSC,2=HFCLK
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ADC1->ULLMEM.CLKFREQ = 7; // 40 to 48 MHz
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ADC1->ULLMEM.CTL0 = 0x03010000;
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// bits 26-24 = 011 divide by 8
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// bit 16 PWRDN=1 for manual, =0 power down on completion, if no pending trigger
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// bit 0 ENC=1 enable (1 to 0 will end conversion)
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ADC1->ULLMEM.CTL1 = 0x00000001;
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// bits 30-28 =0 no shift
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// bits 26-24 =0 no averaging
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// bit 20 SAMPMODE=0 timer triggers
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// bits 17-16 CONSEQ=01 ADC at start will be sampled once, 10 for repeated sampling
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// bit 8 SC=0 for stop, =1 to software start
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// bit 0 TRIGSRC=1 timer trigger
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ADC1->ULLMEM.CTL2 = 0x00000000;
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// bits 28-24 ENDADD (which MEMCTL to end)
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// bits 20-16 STARTADD (which MEMCTL to start)
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// bits 15-11 SAMPCNT (for DMA)
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// bit 10 FIFOEN=0 disable FIFO
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// bit 8 DMAEN=0 disable DMA
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// bits 2-1 RES=0 for 12 bit (=1 for 10bit,=2for 8-bit)
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// bit 0 DF=0 unsigned formant (1 for signed, left aligned)
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ADC1->ULLMEM.MEMCTL[0] = reference+channel;
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// bit 28 WINCOMP=0 disable window comparator
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// bit 24 TRIG trigger policy, =0 for auto next, =1 for next requires trigger
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// bit 20 BCSEN=0 disable burn out current
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// bit 16 = AVGEN =0 for no averaging
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// bit 12 = STIME=0 for SCOMP0
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// bits 9-8 VRSEL = 10 for internal VREF,(00 for VDDA)
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// bits 4-0 channel = 0 to 7 available
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ADC1->ULLMEM.SCOMP0 = 0x64; // sample clocks
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ADC1->ULLMEM.SCOMP1 = 0x32; // sample clocks
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if(reference == ADCVREF_INT){
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VREF->CLKSEL = 0x00000008; // bus clock
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VREF->CLKDIV = 0; // divide by 1
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VREF->CTL0 = 0x0001;
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// bit 8 SHMODE = off
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// bit 7 BUFCONFIG=0 for 2.4 (=1 for 1.4)
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// bit 0 is enable
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VREF->CTL2 = 0;
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// bits 31-16 HCYCLE=0
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// bits 15-0 SHCYCLE=0
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while((VREF->CTL1&0x01)==0){}; // wait for VREF to be ready
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}
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ADC1->ULLMEM.FSUB_0 = 0x00000001; // subscribe to chan 1
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ADC1->ULLMEM.CPU_INT.IMASK = 0x00000100; //MEMRESIFG0
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ADC1->ULLMEM.CTL0 |= 1; // start
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NVIC->ISER[0] = 1 << 5; // ADC1 interrupt
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NVIC->IP[1] = (NVIC->IP[1]&(~0x0000FF00))|(priority<<14); // set priority (bits 15,14) IRQ 5
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TIMG8->COUNTERREGS.CTRCTL |= 0x01;
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}
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