258 lines
9.3 KiB
ArmAsm
258 lines
9.3 KiB
ArmAsm
/* ***************************************************************************
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; osasm.s: low-level OS commands, written in assembly
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; derived from uCOS-II
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;****************************************************************************
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;OS Lab2/3/4/5/6
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;Students will implement these functions as part of ECE445M Lab
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;Starter to labs 1,2,3,4
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; Jonathan Valvano
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; December 21, 2025
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;
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;Copyright 2025 by Jonathan W. Valvano, valvano@mail.utexas.edu
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; You may use, edit, run or distribute this file
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; as long as the above copyright notice remains
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; THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
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; OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
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; MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
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; VALVANO SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
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; OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
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; For more information about my classes, my research, and my books, see
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; http://users.ece.utexas.edu/~valvano/
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;
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*/
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.data
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.align 2
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// Declare global variables here if needed
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// with the .space assembly directive
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.text
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.thumb
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.align 2
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.global RunPt // currently running thread
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.global NextThreadPt // next thread to run, set by schedule
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.global Scheduler
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.global SysTick_Handler
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.global TimeMs
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.global OS_MsTime
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.global OS_ClearMsTime
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.global Scheduler
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.global ReadyLists
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.global RunPts
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.global StartOS
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.global ContextSwitch2
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.global PendSV_Handler
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.global OSDisableInterrupts
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.global OSEnableInterrupts
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.global SVC_Handler
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.global StartCritical
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.global EndCritical
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.include "../inc/msp.s" // For profiling
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.macro TogglePB22
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LDR R0, =GPIOB_DOUTTGL31_0
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LDR R1, =(1 << 22)
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STR R1, [R0]
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.endm
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.equ POINTERSIZE, 4 // bytes
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.equ TCB_NEXT, 4 // offset within struct
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OSDisableInterrupts:
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CPSID I
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BX LR
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OSEnableInterrupts:
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CPSIE I
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BX LR
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// *********** StartCritical ************************
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//make a copy of previous I bit, disable interrupts
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// inputs : none
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// outputs : R0=previous I bit
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StartCritical:
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MRS R0, PRIMASK // save old status
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CPSID I // mask all (except faults)
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BX LR
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// *********** EndCritical ************************
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// using the copy of previous I bit, restore I bit to previous value
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// inputs : R0=previous I bit
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// outputs : none
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EndCritical:
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MSR PRIMASK, R0
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BX LR
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// ******** OS_ClearMsTime ************
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// sets the system time to zero (solve for Lab 1), and start a periodic interrupt
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// Inputs: none
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// Outputs: none
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// You are free to change how this works
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OS_ClearMsTime:
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PUSH {LR}
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BL StartCritical // Save I bit
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LDR R2, =TimeMs
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MOVS R1, #0
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STR R1, [R2]
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BL EndCritical // Restore I bit
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LDR R0, =10000 //period
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MOVS R1, 4 //prescale
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MOVS R2, 1 //priority
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BL TimerG8_IntArm //40MHz Clock - will arm @ 1kHz
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POP {PC}
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// ******** OS_MsTime ************
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// reads the current time in msec (solve for Lab 1)
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// Inputs: none
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// Outputs: time in ms units
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// You are free to select the time resolution for this function
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// For Labs 2 and beyond, it is ok to make the resolution to match the first call to OS_AddPeriodicThread
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OS_MsTime:
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LDR R0, =TimeMs
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LDR R0, [R0]
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BX LR
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// Scheduler handles the algorithm for switching threads
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Scheduler:
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MOVS R0, #0 // priorityReady
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LDR R1, =ReadyLists
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readyListLoop: // Traverse ReadyLists array looking for highest priority thread that is ready
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LDR R2, [R1, R0]
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CMP R2, #0
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BNE readyFound
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ADDS R0, R0, #POINTERSIZE // Keep looking if NULL, will break if no ready threads
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B readyListLoop
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readyFound:
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LDR R1, =RunPts
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ADDS R1, R0 // R1 = RunPts + priorityReady Pointer to TCB pointer
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LDR R0, [R1] // R0 = RunPts[priorityReady] Pointer to actual TCB
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LDR R0, [R0, #TCB_NEXT] // R0 = RunPts[priorityReady]->next
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LDR R2, =RunPt
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STR R0, [R2] // RunPt = RunPts[priorityReady]->next
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STR R0, [R1] // RunPts[priorityReady] = RunPt
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BX LR
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StartOS:
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// put your code here
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LDR R0, =RunPt // Pointer to currently running thread
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LDR R1, [R0] // R1 = value of RunPt
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LDR R2, [R1] // new thread SP
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MOV SP, R2 // Switch stack pointer
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POP {R4-R7} // Restore R4-R7
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POP {R0-R3} // Restore R0-R3
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ADD SP, SP, #8 // Discard R12 and LR
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POP {R0} // start location
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ADD SP, SP, #4 // Discard PSR
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CPSIE I // Enable interrupts
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BX R0 // Start first thread
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OSStartHang:
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B OSStartHang // Should never get here
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/* *******************************************************************************************************
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; HANDLE PendSV EXCEPTION
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; void PendSV_Handler(void)
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;
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; Note(s) : 1) PendSV is used to cause a context switch. This is a recommended method for performing
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; context switches with Cortex-M. This is because the Cortex-M auto-saves half of the
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; processor context on any exception, and restores same on return from exception. So only
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; saving of R4-R7 is required and fixing up the stack pointers. Using the PendSV exception
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; this way means that context saving and restoring is identical whether it is initiated from
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; a thread or occurs due to an interrupt or exception.
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;
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; 2) Pseudo-code is:
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; a) disable interrupts so context switch is atomic
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; b) Push remaining R4-R7 on stack;
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; c) Save the SP in its TCB,
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; d) Get next thread to run from the OS.c
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; e) Load SP of next thread into SP
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; f) Pop R4-R7 from new stack;
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; g) enable interrupts
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; i) Perform exception return which will restore remaining context.
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;
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; 3) On entry into PendSV handler:
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; a) The following have been saved on the process stack (by processor):
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; xPSR, PC, LR, R12, R0-R3
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; b) RunPt points to the tcb of the task to suspend
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; c) NextThreadPt points to the tcb of the task to resume
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;
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; 4) Since PendSV is set to lowest priority in the system, we
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; know that it will only be run when no other exception or interrupt is active, and
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; therefore safe to assume that context being switched out was a user thread and not an ISR.
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;
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; 5) We will assume (hope) the compiler does not use R8-R11
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;
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;********************************************************************************************************/
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.type PendSV_Handler, %function
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// Only ISR running at priority 3 guarantees it interrupts only main/foreground code
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PendSV_Handler:
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// put your code here
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TogglePB22 // For profiling
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TogglePB22 // For profiling
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CPSID I // Prevent interrupt during switch
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PUSH {R4-R7}
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LDR R4, =RunPt
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LDR R1, [R4]
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MOV R2, SP
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STR R2, [R1] // Save SP into old thread's TCB
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MOV R5, LR // Preserve LR when calling scheduler
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BL Scheduler // Call scheduler to pick the next thread
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MOV LR, R5 // Restore LR
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LDR R1, [R4] // R1 = RunPt
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LDR R2, [R1] // SP of new thread
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MOV SP, R2
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POP {R4-R7}
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CPSIE I // Re-enable interrupts
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TogglePB22 // For profiling
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BX LR // Exception return will restore remaining context
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/* *******************************************************************************************************
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; HANDLE SVC EXCEPTION
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; void SVC_Handler(void)
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;
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; Note(s) : SVC is a software-triggered exception to make OS kernel calls from user land.
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; The function ID to call is encoded in the instruction itself, the location of which can be
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; found relative to the return address saved on the stack on exception entry.
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; Function-call paramters in R0..R3 are also auto-saved on stack on exception entry.
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;
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;********************************************************************************************************/
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.type OS_Id, %function
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.type OS_Kill, %function
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.type OS_Sleep, %function
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.type OS_Time, %function
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.type OS_AddThread, %function
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.type ST7735_Message, %function
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.global OS_Id
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.global OS_Kill
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.global OS_Sleep
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.global OS_Time
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.global OS_AddThread
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.global ST7735_Message
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.type SVC_Handler, %function
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SVC_Handler:
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PUSH {R4-R5,LR}
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POP {R4-R5,PC}
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SVCJumpTable:
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.long OS_Id
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.long OS_Kill
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.long OS_Sleep
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.long OS_Time
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.long OS_AddThread
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.long ST7735_Message
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.end
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