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inc/UARTints.c
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167
inc/UARTints.c
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/* UARTints.c
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* Jonathan Valvano
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* November 18, 2022
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* Derived from uart_rw_multibyte_fifo_poll_LP_MSPM0G3507_nortos_ticlang
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* uart_echo_interrupts_standby_LP_MSPM0G3507_nortos_ticlang
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* PA.10 UART0 Tx to XDS Rx
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* PA.11 UART0 Rx from XDS Tx
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* Insert jumper J25: Connects PA10 to XDS_UART
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* Insert jumper J26: Connects PA11 to XDS_UART
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*/
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#include <ti/devices/msp/msp.h>
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#include "../inc/UART.h"
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#include "../inc/Clock.h"
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#include "../inc/FIFO.h"
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#define PA10INDEX 20
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#define PA11INDEX 21
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// power Domain PD0
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// for 32MHz bus clock, bus clock is 32MHz
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// for 40MHz bus clock, bus clock is ULPCLK 20MHz
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// for 80MHz bus clock, bus clock is ULPCLK 40MHz
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// assume 40MHz bus clock, bus clock = 20MHz
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// initialize UART for 115200 baud rate
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// interrupt synchronization
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void UART_Init(void){
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// RSTCLR to GPIOA and UART0 peripherals
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// bits 31-24 unlock key 0xB1
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// bit 1 is Clear reset sticky bit
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// bit 0 is reset gpio port
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// GPIOA->GPRCM.RSTCTL = (uint32_t)0xB1000003; // called previously
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UART0->GPRCM.RSTCTL = 0xB1000003;
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// Enable power to GPIOA and UART0 peripherals
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// PWREN
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// bits 31-24 unlock key 0x26
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// bit 0 is Enable Power
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// GPIOA->GPRCM.PWREN = (uint32_t)0x26000001; // called previously
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UART0->GPRCM.PWREN = 0x26000001;
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Clock_Delay(24); // time for uart to power up
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// configure PA11 PA10 as alternate UART0 function
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IOMUX->SECCFG.PINCM[PA10INDEX] = 0x00000082;
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//bit 7 PC connected
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//bits 5-0=2 for UART0_Tx
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IOMUX->SECCFG.PINCM[PA11INDEX] = 0x00040082;
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//bit 18 INENA input enable
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//bit 7 PC connected
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//bits 5-0=2 for UART0_Rx
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TxFifo_Init();
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RxFifo_Init();
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UART0->CLKSEL = 0x08; // bus clock
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UART0->CLKDIV = 0x00; // no divide
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UART0->CTL0 &= ~0x01; // disable UART0
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UART0->CTL0 = 0x00020018;
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// bit 17 FEN=1 enable FIFO
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// bits 16-15 HSE=00 16x oversampling
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// bit 14 CTSEN=0 no CTS hardware
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// bit 13 RTSEN=0 no RTS hardware
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// bit 12 RTS=0 not RTS
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// bits 10-8 MODE=000 normal
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// bits 6-4 TXE=001 enable TxD
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// bit 3 RXE=1 enable TxD
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// bit 2 LBE=0 no loop back
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// bit 0 ENABLE 0 is disable, 1 to enable
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// 20000000/16 = 1,250,000 Hz
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// Baud = 115200
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/*
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// 1,250,000/115200 = 10.850694
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// divider = 10+54/64 = 10.84375
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UART0->IBRD = 10;
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UART0->FBRD = 54; // baud =1,250,000/10.84375 = 115,274 bps
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*/
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if(Clock_Freq() == 40000000){
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// 20000000/16 = 1,250,000 Hz
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// Baud = 115200
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// 1,250,000/115200 = 10.850694
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// divider = 10+54/64 = 10.84375
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UART0->IBRD = 10;
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UART0->FBRD = 54; // baud =1,250,000/10.84375 = 115,274
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}else if (Clock_Freq() == 32000000){
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// 32000000/16 = 2,000,000
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// Baud = 115200
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// 2,000,000/115200 = 17.361
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// divider = 17+23/64 = 17.359
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UART0->IBRD = 17;
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UART0->FBRD = 23;
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}else if (Clock_Freq() == 80000000){
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// 40000000/16 = 2,500,000 Hz
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// Baud = 115200
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// 2,500,000/115200 = 21.701388
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// divider = 21+45/64 = 21.703125
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UART0->IBRD = 21;
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UART0->FBRD = 45; // baud =2,500,000/21.703125 = 115,191
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}else return;
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UART0->LCRH = 0x00000030;
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// bits 5-4 WLEN=11 8 bits
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// bit 3 STP2=0 1 stop
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// bit 2 EPS=0 parity select
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// bit 1 PEN=0 no parity
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// bit 0 BRK=0 no break
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UART0->CPU_INT.IMASK = 0x0C01;
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// bit 11 TXINT
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// bit 10 RXINT
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// bit 0 Receive timeout
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UART0->IFLS = 0x0422;
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// bits 11-8 RXTOSEL receiver timeout select 4 (0xF highest)
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// bits 6-4 RXIFLSEL 2 is greater than or equal to half
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// bits 2-0 TXIFLSEL 2 is less than or equal to half
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NVIC->ICPR[0] = 1<<15; // UART0 is IRQ 15
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NVIC->ISER[0] = 1<<15;
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NVIC->IP[3] = (NVIC->IP[3]&(~0xFF000000))|(2<<30); // set priority (bits 31,30) IRQ 15
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UART0->CTL0 |= 0x01; // enable UART0
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}
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// copy from hardware RX FIFO to software RX FIFO
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// stop when hardware RX FIFO is empty or software RX FIFO is full
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void static copyHardwareToSoftware(void){
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char letter;
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while(((UART0->STAT&0x04) == 0) && (RxFifo_Size() < (RXFIFOSIZE - 1))){
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letter = UART0->RXDATA;
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RxFifo_Put(letter);
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}
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}
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//------------UART_InChar------------
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// Wait for new serial port input
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// Input: none
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// Output: ASCII code for key typed
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char UART_InChar(void){
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char letter;
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do{
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letter = RxFifo_Get();
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}while(letter==0);
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return(letter);
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}
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// copy from software TX FIFO to hardware TX FIFO
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// stop when software TX FIFO is empty or hardware TX FIFO is full
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void static copySoftwareToHardware(void){
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char letter;
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while(((UART0->STAT&0x80) == 0) && (TxFifo_Size() > 0)){
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letter = TxFifo_Get();
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UART0->TXDATA = letter;
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}
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}
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//------------UART_OutChar------------
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// Output 8-bit to serial port
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// Input: letter is an 8-bit ASCII character to be transferred
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// Output: none
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void UART_OutChar(char data){
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while(TxFifo_Put(data) == 0){};
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UART0->CPU_INT.IMASK &= ~0x0800; // disarm TX FIFO interrupt
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copySoftwareToHardware();
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UART0->CPU_INT.IMASK |= 0x0800; // rearm TX FIFO interrupt
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}
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void UART0_IRQHandler(void){ uint32_t status;
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status = UART0->CPU_INT.IIDX; // reading clears bit in RIS
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if(status == 0x01){ // 0x01 receive timeout
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copyHardwareToSoftware();
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}else if(status == 0x0B){ // 0x0B receive
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copyHardwareToSoftware();
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}else if(status == 0x0C){ // 0x0C transmit
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copySoftwareToHardware();
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if(TxFifo_Size() == 0){ // software TX FIFO is empty
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UART0->CPU_INT.IMASK &= ~0x0800; // disable TX FIFO interrupt
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}
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}
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}
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