208 lines
8.0 KiB
C
208 lines
8.0 KiB
C
/* Timer.c
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* Jonathan Valvano
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* August 12, 2023
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* Derived from timx_timer_mode_periodic_sleep_LP_MSPM0G3507_nortos_ticlang
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* gpio_toggle_output_LP_MSPM0G3507_nortos_ticlang
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*
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*/
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#include <ti/devices/msp/msp.h>
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#include "../inc/Clock.h"
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// power Domain PD0
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// initialize G0/G8 for periodic interrupt
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// for 32MHz bus clock, Timer clock is 32MHz
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// for 40MHz bus clock, Timer clock is ULPCLK 20MHz
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// for 80MHz bus clock, Timer clock is ULPCLK 40MHz
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// frequency = TimerClock/prescale/period
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void TimerG0_IntArm(uint16_t period, uint32_t prescale, uint32_t priority){
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TIMG0->GPRCM.RSTCTL = 0xB1000003;
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TIMG0->GPRCM.PWREN = 0x26000001;
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Clock_Delay(24); // time for TimerG0 to power up
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TIMG0->CLKSEL = 0x08; // bus clock
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TIMG0->CLKDIV = 0x00; // divide by 1
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TIMG0->COMMONREGS.CPS = prescale-1; // divide by prescale,
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TIMG0->COUNTERREGS.LOAD = period-1; // set reload register
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TIMG0->COUNTERREGS.CTRCTL = 0x02;
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// bits 5-4 CM =0, down
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// bits 3-1 REPEAT =001, continue
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// bit 0 EN enable (0 for disable, 1 for enable)
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//TIMG0->INT_EVENT[0].IMASK |= 1; // zero event mask
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TIMG0->CPU_INT.IMASK = 1; // zero event mask
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// TIMG0->GEN_EVENT1.IMASK |= 1; // zero event mask
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TIMG0->COMMONREGS.CCLKCTL = 1;
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NVIC->ISER[0] = 1 << 16; // TIMG0 interrupt
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NVIC->IP[4] = (NVIC->IP[4]&(~0x000000FF))|(priority<<6); // set priority (bits 7,6) IRQ 16
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TIMG0->COUNTERREGS.CTRCTL |= 0x01;
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}
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// frequency = TimerClock/prescale/period
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void TimerG8_IntArm(uint16_t period, uint32_t prescale, uint32_t priority){
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TIMG8->GPRCM.RSTCTL = 0xB1000003;
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TIMG8->GPRCM.PWREN = 0x26000001;
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Clock_Delay(24); // time for TimerG8 to power up
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TIMG8->CLKSEL = 0x08; // bus clock
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TIMG8->CLKDIV = 0x00; // divide by 1
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TIMG8->COMMONREGS.CPS = prescale-1; // divide by prescale,
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TIMG8->COUNTERREGS.LOAD = period-1; // set reload register
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TIMG8->COUNTERREGS.CTRCTL = 0x02;
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// bits 5-4 CM =0, down
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// bits 3-1 REPEAT =001, continue
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// bit 0 EN enable (0 for disable, 1 for enable)
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TIMG8->CPU_INT.IMASK |= 1; // zero event mask
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TIMG8->COMMONREGS.CCLKCTL = 1;
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NVIC->ISER[0] = 1 << 2; // TIMG8 interrupt
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NVIC->IP[0] = (NVIC->IP[0]&(~0x00FF0000))|(priority<<22); // set priority (bits 23,22) IRQ 2
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TIMG8->COUNTERREGS.CTRCTL |= 0x01;
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}
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// Power Domain PD1
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// initialize A0/A1/G6/G7/G12 for periodic interrupt
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// for 32MHz bus clock, Timer clock is 32MHz
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// for 40MHz bus clock, Timer clock is MCLK 40MHz
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// for 80MHz bus clock, Timer clock is MCLK 80MHz
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// frequency = TimerClock/prescale/period
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void TimerA0_IntArm(uint16_t period, uint32_t prescale, uint32_t priority){
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TIMA0->GPRCM.RSTCTL = (uint32_t)0xB1000003;
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TIMA0->GPRCM.PWREN = (uint32_t)0x26000001;
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Clock_Delay(24); // time for TimerA0 to power up
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TIMA0->CLKSEL = 0x08; // bus clock
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TIMA0->CLKDIV = 0x00; // divide by 1
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TIMA0->COMMONREGS.CPS = prescale-1; // divide by prescale,
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TIMA0->COUNTERREGS.LOAD = period-1; // set reload register
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TIMA0->COUNTERREGS.CTRCTL = 0x02;
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// bits 5-4 CM =0, down
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// bits 3-1 REPEAT =001, continue
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// bit 0 EN enable (0 for disable, 1 for enable)
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TIMA0->CPU_INT.IMASK |= 1; // zero event mask
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TIMA0->COMMONREGS.CCLKCTL = 1;
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NVIC->ISER[0] = 1 << 18; // TIMA0 interrupt
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NVIC->IP[4] = (NVIC->IP[4]&(~0x00FF0000))|(priority<<22); // set priority (bits 23,22) IRQ 18
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TIMA0->COUNTERREGS.CTRCTL |= 0x01;
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}
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// initialize A1 for periodic interrupt
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// frequency = TimerClock/prescale/period
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void TimerA1_IntArm(uint16_t period, uint32_t prescale, uint32_t priority){
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TIMA1->GPRCM.RSTCTL = (uint32_t)0xB1000003;
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TIMA1->GPRCM.PWREN = (uint32_t)0x26000001;
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Clock_Delay(2); // time for TimerA1 to power up
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TIMA1->CLKSEL = 0x08; // bus clock
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TIMA1->CLKDIV = 0x00; // divide by 1
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TIMA1->COMMONREGS.CPS = prescale-1; // divide by prescale
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TIMA1->COUNTERREGS.LOAD = period-1; // set reload register
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TIMA1->COUNTERREGS.CTRCTL = 0x02;
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// bits 5-4 CM =0, down
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// bits 3-1 REPEAT =001, continue
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// bit 0 EN enable (0 for disable, 1 for enable)
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TIMA1->CPU_INT.IMASK |= 1; // zero event mask
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TIMA1->COMMONREGS.CCLKCTL = 1;
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NVIC->ISER[0] = 1 << 19; // TIMA1 interrupt
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NVIC->IP[4] = (NVIC->IP[4]&(~0xFF000000))|(priority<<30); // set priority (bits 31,30) IRQ 19
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TIMA1->COUNTERREGS.CTRCTL |= 0x01;
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}
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// initialize G7 for periodic interrupt
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// frequency = TimerClock/prescale/period
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void TimerG7_IntArm(uint16_t period, uint32_t prescale, uint32_t priority){
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TIMG7->GPRCM.RSTCTL = (uint32_t)0xB1000003;
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TIMG7->GPRCM.PWREN = (uint32_t)0x26000001;
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Clock_Delay(24); // time for TimerG7 to power up
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TIMG7->CLKSEL = 0x08; // bus clock
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TIMG7->CLKDIV = 0x00; // divide by 1
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TIMG7->COMMONREGS.CPS = prescale-1; // divide by prescale
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TIMG7->COUNTERREGS.LOAD = period-1; // set reload register
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TIMG7->COUNTERREGS.CTRCTL = 0x02;
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// bits 5-4 CM =0, down
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// bits 3-1 REPEAT =001, continue
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// bit 0 EN enable (0 for disable, 1 for enable)
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TIMG7->CPU_INT.IMASK |= 1; // zero event mask
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TIMG7->COMMONREGS.CCLKCTL = 1;
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NVIC->ISER[0] = 1 << 20; // TIMG7 interrupt
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NVIC->IP[5] = (NVIC->IP[5]&(~0x000000FF))|(priority<<6); // set priority (bits 7,6) IRQ 20
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TIMG7->COUNTERREGS.CTRCTL |= 0x01;
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}
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// initialize G6 for periodic interrupt
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// frequency = TimerClock/prescale/period
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void TimerG6_IntArm(uint16_t period, uint32_t prescale, uint32_t priority){
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TIMG6->GPRCM.RSTCTL = (uint32_t)0xB1000003;
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TIMG6->GPRCM.PWREN = (uint32_t)0x26000001;
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Clock_Delay(24); // time for TimerG6 to power up
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TIMG6->CLKSEL = 0x08; // bus clock
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TIMG6->CLKDIV = 0x00; // divide by 1
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TIMG6->COMMONREGS.CPS = prescale-1; // divide by prescale
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TIMG6->COUNTERREGS.LOAD = period-1; // set reload register
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TIMG6->COUNTERREGS.CTRCTL = 0x02;
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// bits 5-4 CM =0, down
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// bits 3-1 REPEAT =001, continue
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// bit 0 EN enable (0 for disable, 1 for enable)
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TIMG6->CPU_INT.IMASK |= 1; // zero event mask
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TIMG6->COMMONREGS.CCLKCTL = 1;
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NVIC->ISER[0] = 1 << 17; // TIMG6 interrupt
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NVIC->IP[4] = (NVIC->IP[4]&(~0x0000FF00))|(priority<<14); // set priority (bits 15,14) IRQ 17
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TIMG6->COUNTERREGS.CTRCTL |= 0x01;
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}
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// initialize G12 for periodic interrupt, 32 bit
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// no prescale
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// frequency = TimerClock/period
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void TimerG12_IntArm(uint32_t period, uint32_t priority){
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TIMG12->GPRCM.RSTCTL = (uint32_t)0xB1000003;
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TIMG12->GPRCM.PWREN = (uint32_t)0x26000001;
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Clock_Delay(24); // time for TimerG12 to power up
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TIMG12->CLKSEL = 0x08; // bus clock
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TIMG12->CLKDIV = 0x00; // divide by 1
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TIMG12->COUNTERREGS.LOAD = period-1; // set reload register
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TIMG12->COUNTERREGS.CTRCTL = 0x02;
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// bits 5-4 CM =0, down
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// bits 3-1 REPEAT =001, continue
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// bit 0 EN enable (0 for disable, 1 for enable)
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TIMG12->CPU_INT.IMASK |= 1; // zero event mask
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TIMG12->COMMONREGS.CCLKCTL = 1;
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NVIC->ISER[0] = 1 << 21; // TIMG12 interrupt
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NVIC->IP[5] = (NVIC->IP[5]&(~0x0000FF00))|(priority<<14); // set priority (bits 15,14) IRQ 21
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TIMG12->COUNTERREGS.CTRCTL |= 0x01;
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}
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// initialize G12 for continuous counting
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// simply read TIMG12->COUNTERREGS.CTR for 32 bit time
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// resolution is bus clock
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// precision is 32 bits
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// for 80 MHz clock, 12.5ns
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// power Domain PD1 for G12
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// for 32MHz bus clock, Timer clock is 32MHz
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// for 40MHz bus clock, Timer clock is ULPCLK 40MHz
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// for 80MHz bus clock, Timer clock is ULPCLK 80MHz
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void TimerG12_Init(void){
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TIMG12->GPRCM.RSTCTL = (uint32_t)0xB1000003;
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TIMG12->GPRCM.PWREN = (uint32_t)0x26000001;
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Clock_Delay(24); // time for TimerG8 to power up
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TIMG12->CLKSEL = 0x08; // bus clock
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TIMG12->CLKDIV = 0; // divide by 1
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// TIMG8->COMMONREGS.CPS = prescale-1; // divide by prescale,
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TIMG12->COUNTERREGS.LOAD = 0xFFFFFFFF; // set reload register
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TIMG12->COUNTERREGS.CTRCTL = 0x02;
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// bits 5-4 CM =0, down
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// bits 3-1 REPEAT =001, continue
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// bit 0 EN enable (0 for disable, 1 for enable)
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TIMG12->COMMONREGS.CCLKCTL = 1;
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TIMG12->COUNTERREGS.CTRCTL |= 0x01;
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}
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