130 lines
5.7 KiB
C
130 lines
5.7 KiB
C
/* PWMA0.c
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* Jonathan Valvano
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* November 24, 2025
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* Derived from timx_timer_mode_pwm_edge_sleep_LP_MSPM0G3507_nortos_ticlang
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*/
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/*
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* Copyright (c) 2026, Texas Instruments Incorporated
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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*
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* * Neither the name of Texas Instruments Incorporated nor the names of
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* its contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
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* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
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* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
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* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
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* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <ti/devices/msp/msp.h>
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#include "../inc/LaunchPad.h"
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#include "../RTOS_Labs_common/PWMA0.h"
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#include "../inc/Clock.h"
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// Timer A0 is on Power domain PD1
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// for 32MHz bus clock, Timer clock is 32MHz
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// for 40MHz bus clock, Timer clock is MCLK 40MHz
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// for 80MHz bus clock, Timer clock is MCLK 80MHz
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// CCP0 PWM output on PB8
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// CCP1 PWM output on PB9
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// PB8/TIMA0_C0;
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// PB9/TIMA0_C1;
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uint32_t PWMA0_Period;
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// Initialize PWM outputs on PA12 PA13
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// Rising edge synchronized
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// timerClkSrc = 2 for 32768 Hz LFCLK
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// = 4 for 4MHz MFCLK
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// = 8 for 80/40/32/4 BUSCLK
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// divide clock by timerClkPrescale+1, 0 to 255
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// period sets the PWM period
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// timerClkSrc could be 40MHz, 32MHz, 4MHz, or 32767Hz
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// timerClkDivRatio = 1
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// PWMFreq = (timerClkSrc / (timerClkDivRatio * (timerClkPrescale + 1) * period))
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// For example, source=LFCLK, prescale=0, period = 1000, PWM frequency = 32.768 Hz
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// For example, source=BUSCLK, 80MHz bus, prescale=39, period = 10000, PWM frequency = 200Hz
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void PWMA0_Init(uint32_t timerClkSrc, uint32_t timerClkPrescale, uint32_t period, uint32_t duty0, uint32_t duty1){
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TIMA0->GPRCM.RSTCTL = (uint32_t)0xB1000003;
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TIMA0->GPRCM.PWREN = (uint32_t)0x26000001;
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Clock_Delay(2); // time for TimerA0 to power up
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IOMUX->SECCFG.PINCM[PB8INDEX] = 0x00000084; // TIMA0 output CCP0
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IOMUX->SECCFG.PINCM[PB9INDEX] = 0x00000084; // TIMA0 output CCP1
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GPIOB->DOE31_0 |= (1<<8)|(1<<9);
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TIMA0->CLKSEL = timerClkSrc; // 8=BUSCLK, 4= MFCLK, 2= LFCLK clock
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TIMA0->CLKDIV = 0x00; // divide by 1
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TIMA0->COMMONREGS.CPS = timerClkPrescale; // divide by prescale+1,
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// 32768Hz/256 = 256Hz, 7.8125
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TIMA0->COUNTERREGS.LOAD = period-1; // reload register sets period
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PWMA0_Period = period;
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TIMA0->COUNTERREGS.CTRCTL = 0x02;
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// bits 5-4 CM =0, down
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// bits 3-1 REPEAT =001, continue
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// bit 0 EN enable (0 for disable, 1 for enable)
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TIMA0->COUNTERREGS.CCCTL_01[0] = 0; // no capture
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TIMA0->COUNTERREGS.CCCTL_01[1] = 0; // no capture
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// COC compare mode
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TIMA0->GEN_EVENT0.IMASK = 0x00; // no interrupts
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TIMA0->COMMONREGS.CCPD = 0x03; // output CCP1 CCP0
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TIMA0->COMMONREGS.CCLKCTL = 1;
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TIMA0->COUNTERREGS.CC_01[0] = duty0;
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TIMA0->COUNTERREGS.CC_01[1] = duty1;
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TIMA0->COUNTERREGS.OCTL_01[0] = 0x0000; // connected to PWM
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TIMA0->COUNTERREGS.OCTL_01[1] = 0x0000; // connected to PWM
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TIMA0->COUNTERREGS.CCACT_01[0] = 0x0088;
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TIMA0->COUNTERREGS.CCACT_01[1] = 0x0088;
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// bits 10-9 CUACT 0 for no action on up compare
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// bits 7-6 CDACT 10 for make low on compare event down
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// bits 4-3 LACT 01 for make high on load event
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// bits 1-0 ZACT 00 for no action on zero event
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TIMA0->COUNTERREGS.CTRCTL |= 0x01;
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}
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void PWMA0_SetDuty(uint32_t duty0, uint32_t duty1){
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IOMUX->SECCFG.PINCM[PB8INDEX] = 0x00000084; // PB8 TIMA0 output CCP0 PWM low
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IOMUX->SECCFG.PINCM[PB9INDEX] = 0x00000084; // PB9 TIMA0 output CCP1 PWM low
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TIMA0->COUNTERREGS.CC_01[0] = duty0;
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TIMA0->COUNTERREGS.CC_01[1] = duty1;
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}
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void PWMA0_Forward(uint32_t duty0){
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IOMUX->SECCFG.PINCM[PB8INDEX] = 0x00000084; // PB8 TIMA0 output CCP0 PWM low
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IOMUX->SECCFG.PINCM[PB9INDEX] = 0x00000081; // PB9 GPIO=high
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GPIOB->DOUTSET31_0 = 1<<9; // PB9=1
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TIMA0->COUNTERREGS.CC_01[0] = duty0;
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}
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void PWMA0_Backward(uint32_t duty1){
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IOMUX->SECCFG.PINCM[PB8INDEX] = 0x00000081; // PB8 GPIO=high
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IOMUX->SECCFG.PINCM[PB9INDEX] = 0x00000084; // PB9 TIMA0 output CCP1 PWM low
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GPIOB->DOUTSET31_0 = 1<<8; // PB8=1
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TIMA0->COUNTERREGS.CC_01[1] = duty1;
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}
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void PWMA0_Break(void){
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IOMUX->SECCFG.PINCM[PB8INDEX] = 0x00000081; // PB8 GPIO=high
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IOMUX->SECCFG.PINCM[PB9INDEX] = 0x00000081; // PB9 GPIO=high
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GPIOB->DOUTSET31_0 = (1<<8)|(1<<9); // PB8=1,PB9=1
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}
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void PWMA0_Coast(void){ // will sleep after 1ms
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IOMUX->SECCFG.PINCM[PB8INDEX] = 0x00000081; // PB8 GPIO=high
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IOMUX->SECCFG.PINCM[PB9INDEX] = 0x00000081; // PB9 GPIO=high
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GPIOB->DOUTCLR31_0 = (1<<8)|(1<<9); // PB8=0,PB9=0
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}
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