129 lines
4.3 KiB
C
129 lines
4.3 KiB
C
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/*!
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* @defgroup PWM
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* @brief Pulse width modulation
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<table>
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<caption id="PWMpins">PWM pins on the MSPM0G3507</caption>
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<tr><th>Pin <th>Description
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<tr><td>PA12 <td>CCP0 PWM output
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<tr><td>PA13 <td>CCP1 PWM output
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</table>
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* @{*/
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/**
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* @file PWM.h
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* @brief Pulse width modulation
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* @details Hardware creates fixed period, variable duty cycle waves
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* \image html PWM_100Hz.png width=500px
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* @version ECE319K v1.0
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* @author Daniel Valvano and Jonathan Valvano
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* @copyright Copyright 2023 by Jonathan W. Valvano, valvano@mail.utexas.edu,
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* @warning AS-IS
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* @note For more information see http://users.ece.utexas.edu/~valvano/
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* @date August 13, 2023
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<table>
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<caption id="PWMpins2">PWM pins on the MSPM0G3507</caption>
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<tr><th>Pin <th>Description
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<tr><td>PA12 <td>CCP0 PWM output
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<tr><td>PA13 <td>CCP1 PWM output
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</table>
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******************************************************************************/
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/*
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* Derived from timx_timer_mode_pwm_edge_sleep_LP_MSPM0G3507_nortos_ticlang
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*/
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#ifndef __PWM_H__
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#define __PWM_H__
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/**
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* \brief use PWMUSELFCLK to select LFCLK
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*/
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#define PWMUSELFCLK 2
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/**
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* \brief use PWMUSEMFCLK to select MFCLK
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*/
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#define PWMUSEMFCLK 4
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/**
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* \brief use PWMUSEBUSCLK to select bus CLK
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*/
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#define PWMUSEBUSCLK 8
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/**
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* Initialize PWM outputs on PA12 PA13.
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* Rising edge synchronized. timerClkDivRatio = 1.
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* Once started, hardware will continuously output the waves.
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* - timerClkSrc =
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* - 2 for 32768 Hz LFCLK
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* - 4 for 4MHz MFCLK (not tested)
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* - 8 for 80/32/4 BUSCLK
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* - G0/G8 is on Power domain PD0
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* - 32MHz bus clock, BUSCLK clock is 32MHz
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* - 40MHz bus clock, BUSCLK clock is ULPCLK 20MHz
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* - 80MHz bus clock, BUSCLK clock is ULPCLK 40MHz
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* - PWMFreq = (timerClkSrc / (timerClkDivRatio * (timerClkPrescale + 1) * period))
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* - For example, source=LFCLK, prescale = 0, period = 1000, PWM frequency = 32.768 Hz
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* - For example, source=BUSCLK, bus=40MHz, prescale=19, period = 10000, PWM frequency = 10kHz
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*
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* @param timerClkSrc is 2 4 or 8
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* @param timerClkPrescale divide clock by timerClkPrescale+1, 0 to 255
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* @param period sets the PWM period
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* @param duty0 sets the duty cycle on PA12
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* @param duty1 sets the duty cycle on PA13
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* @return none
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* @note Will call LaunchPad_Init to reset and activate power
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* @see PWM_SetDuty
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* @brief Initialize PWM
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*/
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void PWM_Init(uint32_t timerClkSrc, uint32_t timerClkPrescale,
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uint32_t period, uint32_t duty0, uint32_t duty1);
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/**
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* Set duty cycles on PA12 PA13.
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* @param duty0 sets the duty cycle on PA12
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* @param duty1 sets the duty cycle on PA13
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* @return none
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* @note assumes PWM_Init was called
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* @see PWM_Init
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* @brief Set duty cycles
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*/
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void PWM_SetDuty(uint32_t duty0, uint32_t duty1);
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/**
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* Initialize PWM outputs on PA12 .
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* Rising edge synchronized. timerClkDivRatio = 1.
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* Once started, hardware will continuously output the waves.
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* - timerClkSrc =
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* - 2 for 32768 Hz LFCLK
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* - 4 for 4MHz MFCLK (not tested)
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* - 8 for 80/32/4 BUSCLK
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* - G0/G8 is on Power domain PD0
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* - 32MHz bus clock, BUSCLK clock is 32MHz
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* - 40MHz bus clock, BUSCLK clock is ULPCLK 20MHz
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* - 80MHz bus clock, BUSCLK clock is ULPCLK 40MHz
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* - PWMFreq = (timerClkSrc / (timerClkDivRatio * (timerClkPrescale + 1) * period))
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* - For example, source=LFCLK, prescale = 0, period = 1000, PWM frequency = 32.768 Hz
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* - For example, source=BUSCLK, bus=40MHz, prescale=19, period = 10000, PWM frequency = 10kHz
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*
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* @param timerClkSrc is 2 4 or 8
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* @param timerClkPrescale divide clock by timerClkPrescale+1, 0 to 255
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* @param period sets the PWM period
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* @param duty0 sets the duty cycle on PA12
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* @return none
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* @note Will call LaunchPad_Init to reset and activate power
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* @see PWM_SetDuty
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* @brief Initialize PWM
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*/
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void PWM_PA12Init(uint32_t timerClkSrc, uint32_t timerClkPrescale,
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uint32_t period, uint32_t duty0);
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/**
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* Set duty cycles on PA12 .
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* @param duty0 sets the duty cycle on PA12
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* @return none
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* @note assumes PWM_Init was called
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* @see PWM_Init
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* @brief Set duty cycles
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*/
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void PWM_PA12SetDuty(uint32_t duty0);
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#endif // __PWM_H__
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/** @}*/
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