72 lines
2.1 KiB
C
72 lines
2.1 KiB
C
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/* DAC.c
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* Jonathan Valvano
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* November 30, 2022
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* Derived from dac12_fixed_voltage_vref_internal_LP_MSPM0G3507_nortos_ticlang
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* dac12_fifo_timer_event_LP_MSPM0G3507_nortos_ticlang
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*/
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// PA15 J3.30 DACout
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#include <ti/devices/msp/msp.h>
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#include "../inc/DAC.h"
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#include "../inc/Clock.h"
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// Assumes 40 or 80 MHz MHz bus
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void DAC_Init(void){
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// Reset DAC and VREF
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// RSTCLR
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// bits 31-24 unlock key 0xB1
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// bit 1 is Clear reset sticky bit
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// bit 0 is reset ADC
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VREF->GPRCM.RSTCTL = 0xB1000003;
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DAC0->GPRCM.RSTCTL = 0xB1000003;
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// Enable power ADC and VREF
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// PWREN
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// bits 31-24 unlock key 0x26
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// bit 0 is Enable Power
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VREF->GPRCM.PWREN = 0x26000001;
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DAC0->GPRCM.PWREN = 0x26000001;
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Clock_Delay(24); // time for ADC and VREF to power up
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VREF->CLKSEL = 0x00000008; // bus clock
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VREF->CLKDIV = 0; // divide by 1
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VREF->CTL0 = 0x0001;
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// bit 8 SHMODE = off
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// bit 7 BUFCONFIG=0 for 2.5 (=1 for 1.4)
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// bit 0 is enable
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VREF->CTL2 = 0;
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// bits 31-16 HCYCLE=0
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// bits 15-0 SHCYCLE=0
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while((VREF->CTL1&0x01)==0){}; // wait for VREF to be ready
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// CTL0
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// bit 16 DFM 0 straight binary
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// bit 8 RES 1 12-bit
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// bit 0 ENABLE 1 for on, 0 for disable
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DAC0->CTL0 = 0x0100; // 12-bit, straight, disable
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// CTL1
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// bit 24 OPS 1 OUT0 is selected
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// bit 9 REFSN 0 VR- is VrefN, 1 for analog ground
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// bit 8 REFSP 1 VR+ is VrefP, 0 for analog supply
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// bit 1 AMPHIZ 0 HiZ when disabled
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// bit 0 AMPEN 1 enabled
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DAC0->CTL1 = (1<<24)|(1<<9)|(1<<8)|1;
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// DAC0->CTL1 = (1<<24)|(1<<9)|1;
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DAC0->CTL2 = 0; // no DMA, no FIFO trigger
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// CTL3
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// bits 11-8 STIMCONFIG n=0 for 500 sps
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// for n = 0 to 5 500*2^n sps (500 to 16k)
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// n=6 100 ksps
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// n=7 200 ksps
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// n=8 500 ksps
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// n=9 1 Msps
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// bit 0 STIMEN =0 disable sample time generator
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DAC0->CTL3 = 0x0700; // no sample time generator
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DAC0->CTL0 = 0x0101; // 12-bit, straight, enable
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}
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// output to 12-bit DAC
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void DAC_Out(uint32_t data){
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DAC0->DATA0 = data;
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}
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